In the following descriptions, the placement object (the placement object block) signifies a logic function unit taking a part of the function of a semiconductor integrated circuit that is an object of floorplanning. The logic function unit corresponds to, for example, a user logic circuit (for example, sub-chip) whose position, shape and dimensions can be changed, or a mounting block (for example, LSG (Layout Sub Group) block) obtained by dividing the user logic circuit into mounting hierarchies (mounting regions).
More specifically, as shown in FIG. 32, when a semiconductor integrated circuit (Chip) 110 that is an object of floorplanning has external I/O areas (External I/O Area) 111 and a plurality of sub-chips (Sub Chip) 112, and, further, each of the plural sub-chips 112 has a plurality of mounting blocks 113 each having a plurality of internal components (devices; for example, RAM (Random Access Memory), ROM (Read Only Memory), and standard cell (Standard Cell)), the sub chip 112 or the mounting block 113 is a placement object.
Accordingly, as shown in FIGS. 33(a) to 33(c), when floorplanning at a level of the sub-chip 112 is executed, the mounting block 113 is the placement object (refer to FIGS. 33(b) and 33(c)), and when the floorplanning at a level of the semiconductor integrated circuit 110 is executed, the sub-chip 112 is the placement object (refer to FIGS. 33(a) and 33(b)).
Conventionally, when a floorplanning apparatus for semiconductor integrated circuit (for example, LSI: (Large Scale Integrated circuit)) arranges a plurality of placement objects (placement object blocks) 102 to 105 in a placement region of the semiconductor integrated circuit 100, the floorplanning apparatus forms the placement objects 102 to 105 into rectangles and avoids overlap of the plural placement objects 102 to 105 each other, as shown in FIG. 34, for example. Incidentally, rectangular regions painted black in FIG. 34 and FIG. 35 to be described later designate internal components in the placement objects 102 to 105.
However, when the placement objects are given rectangular shapes, the areas of the placement objects 102 to 105 are increased because of placement and wiring constraints of internal components (internal cells; for example, RAM; Random Access Memory, ROM; Read Only Memory, standard cell) of the placement objects 102 to 105. This results in that the areas of the placement objects 102 to 105 are increased which leads to an increase in area of the whole semiconductor integrated circuit 100, and in that it becomes difficult that the timing of the semiconductor integrated circuit 100 falls within the prescribed cycle time (first problem).
When the placement objects 102 to 105 take rectangular shapes, a difference in density of the internal components in the placement objects becomes large due to shapes, dimensions and the number of the internal components as shown, particularly, in the placement objects 102 and 103, which causes an increase of dead spaces (second problem).
To overcome the aforementioned problems, there has been proposed a floorplanning apparatus that designs the placement objects 102′ to 105′ by giving a variety of arbitrary non-rectangular shapes (here, rectangular polygons) thereto, thereby to prevent the placement objects 102′ to 105′ from overlapping each other, as shown in FIG. 35. This floorplanning apparatus can provide a semiconductor integrated circuit 100′ smaller in size than the semiconductor integrated circuit 100 while arranging placement objects 102′ to 105′ having the same internal components as those of the placement objects 102 to 105 shown in FIG. 34. As a result, this floorplanning apparatus can solve the above first and second problems.
To meet requirements for introduction of hierarchical layout of design, facility for design or down-sizing of semiconductor integrated circuits with an increase in scale or an increase in density of semiconductor integrated circuits, there has been provided a floorplanning apparatus which allows rectangular placement objects and non-rectangular placement objects to mingle. This floorplanning apparatus determines the order of arrangement of placement objects according to priorities of timing limitation, the number of wires, etc. to prevent a placement object from being placed on another placement object that was placed earlier than this placement object, thereby avoiding occurrence of overlap of the placement objects.
As the floorplanning technique for semiconductor integrated circuits, there have been proposed a technique of dividing a rectangular polygon generated on a layout surface into a minimum number of rectangular areas in order to shorten the design period of an integrated circuit (for example, refer to Patent Document 1 below), and a technique of preparing mask lithographic data of mask for exposing electron beams, for performing electron beam lithographic by dividing a pattern of a polygon into rectangle patterns (for example, refer to Patent Document 2 below).    Patent Document 1: Japanese Patent Laid-Open (Kokai) No. 2000-20566    Patent Document 2: Japanese Patent Laid-Open (Kokai) No. 2003-45780